1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, a semiconductor device for performing data bus inversion (DBI) operation and method of operating the same.
2. Description of the Related Art
A lot of signals are transferred between a semiconductor device and a controller for the semiconductor device through a path that is referred to as a channel. A channel transfers various types of signals. There may be a concern during transfer of the signals under circumstance of high speed operation of the semiconductor device. For example, the semiconductor device may consume large amount of current and there may be a high probability of error when a signal on the channel toggles between a low level and a high level a lot.
Data bus inversion (DBI) is nowadays introduced to overcome the problem. The DBI reduces a number of toggles or state transitions of the signals. According to the DBI, when a signal of 8-bit data is to be transferred, for example, it is checked a number of data shifting to a low level. All of the data is shifted to the low level when the number of data shifting to the low level exceeds 4. Accordingly, the DBI does not allow the number of data shifting from a high level to the low level to exceed 4 when a signal of 8-bit data is to be transferred.
FIG. 1 is a block diagram illustrating a conventional semiconductor device.
Referring to FIG. 1, the semiconductor device includes a command decoder 110, an address buffer 120, a multipurpose register 130, a core region 140, a DBI calculator 150 and a multiplexer 160.
The command decoder 110 decodes external command signals ‘/CS’, ‘/RAS’, ‘/CAS’ and ‘/WE’ and generates a multipurpose register (MPR) signal MPREN, a MPR read signal MPR_RD and MPR write signal MPR_WR for controlling the multipurpose register 130. The MPR signal MPREN is one for controlling enablement operation of the multipurpose register 130. The MPR write signal MPR_WR is one for controlling write operation of the multipurpose register 130. The MPR read signal MPR_RD is one for controlling read operation of the multipurpose register 130.
The address buffer 120 buffers and outputs a bank address signal BA[1:0] and an address signal A[7:0].
The multipurpose register 130 stores the data buffered and output by the address buffer 120 in response to the MPR write signal MPR_WR and outputs the stored data D[7:0] in response to the MPR read signal MPR_RD.
The core region 140 is connected to global transmission lines GIO[63:0] and receives and outputs data through the global transmission lines GIO[63:0].
The DBI calculator 150 in response to a DBI signal DBIEN calculates DBI information for data received through the global transmission lines GIO[63:0], generates a DBI flag signal DBI[7:0], reflects the DBI flag signal DBI[7:0] to data transferred through the global transmission lines GIO[63:0] and output the data, to which the DBI flag signal DBI[7:0] is reflected, with or without data inversion.
All of the data transferred through the global transmission lines GIO[63:0] during a normal operation may be input to the DBI calculator 150. Hereinafter, description is made with a part, for example, the global transmission lines GIO[7:0] of the global transmission lines GIO[63:0] as an example for clear description.
The DBI calculator 150 includes a DBI flag generation unit 151 and a data inversion unit 152. The DBI flag generation unit 151 in response to the DBI signal DBIEN calculates the DBI information for data D[7:0] received through the global transmission lines GIO[7:0] of the global transmission lines GIO[63:0] and generates the DBI flag signal DBI[7:0]. The data inversion unit 152 outputs the data D[7:0] transferred through the global transmission lines GIO[7:0] of the global transmission lines GIO[63:0] with or without data inversion according to the DBI flag signal DBI[7:0]. The DBI flag signal DBI[7:0] is output from the DBI flag generation unit 151 through a second channel CH_OUT2.
The multiplexer 160 selectively outputs data from the global transmission lines GIO[63:0] or data from the data inversion unit 152 through a first channel CH_OUT1 according to the DBI signal DBIEN.
Detailed description of an operation of the semiconductor device is set forth here below.
FIG. 2 is a timing diagram illustrating write operation of the multipurpose register of the conventional semiconductor device.
Referring to FIG. 2, the MPR signal MPREN is enabled when a mode register setting (MRS) mode is selected in response to the command signal CMD such as ‘/CS’, ‘/RAS’, ‘/CAS’, ‘/WE’ and so forth. The multipurpose register 130 performs write operation during MPR write mode WR that is subsequently selected.
When the MPR write mode WR is selected and the bank address signal BA[1:0] is input, the multipurpose register 130 stores the address signal A[7:0] at a location therein that is selected through the bank address signal BA[1:0]. The multipurpose register 130 comprises a first to fourth registers MPR_LAT1, MPR_LAT2, MPR_LAT3 and MPR_LAT4. The first to fourth register MPR_LAT1 to MPR_LAT4 are selected according to the bank address signal BA[1:0] and, for example, data “F0” is stored into the first register MPR_LAT1, data “0F” is stored into the second register MPR_LAT2, data “00” is stored into the third register MPR_LAT3 and data “FF” is stored into the fourth register MPR_LAT4 according to the address signal A[7:0].
FIG. 3 is a timing diagram illustrating read operation of the multipurpose register without the DBI.
Referring to FIG. 3, the MPR signal MPREN is enabled when the MRS mode is selected in response to the command signal CMD. The multipurpose register 130 performs read operation during MPR read mode RD that is subsequently selected.
When the MPR read mode RD is selected, data D[7:0] stored in the first to fourth register MPR_LAT1 to MPR_LAT4 are output to the first channel CH_OUT1 through the global transmission lines GIO[7:0] of the global transmission lines GIO[63:0].
FIG. 4 is a timing diagram illustrating read operation of the multipurpose register with the DBI.
Referring to FIG. 4, data to be output to the first channel CH_OUT1 is inverted according to the DBI when the majority of the data has the low level.
Training operation between the semiconductor device and the controller becomes one of major concerns as data transmission speed between the semiconductor device and the controller gets higher nowadays.
Referring back to FIG. 3 illustrating conventional operation without the DBI, it is possible to perform the data training operation to the first channel CH_OUT1 but impossible to perform the data training operation to the second channel CH_OUT2 due to absence of the DBI.
Referring back to FIG. 4 illustrating operation with the DBI, it is possible to perform the data training operation to the second channel CH_OUT2 but impossible to perform the data training operation to the first channel CH_OUT1 because all of data output from the first channel CH_OUT1 have the high level by DBI information of the DBI operation.
In short, in the conventional semiconductor device, it is possible to perform the data training operation to the first channel CH_OUT1 but impossible to perform the data training operation to the second channel CH_OUT2 due to absence of the DBI. On the other hand, it is possible to perform the data training operation to the second channel CH_OUT2 but impossible to perform the data training operation to the first channel CH_OUT1 due to presence of the DBI.